1. Field of the Invention
The present invention relates to a semiconductor memory and a method of writing, reading, and sustaining data thereof, and more particularly, to a semiconductor memory such as an SRAM (static random access memory) having memory cells each made of a resonance-tunnel-hot-electron transistor having a negative differential characteristic and a threshold characteristic and a method of writing, reading, and sustaining data thereof.
2. Description of the Related Art
In recent years, large-scale semiconductor memories such as 256-Mbit DRAMs (dynamic random access memories) and 64-Mbit SRAMs are being developed. Conventional memory cell structures are incapable of realizing higher density memories. Therefore, it is required to provide semiconductor memory cells suitable for forming high-density memories as well as a method of stably driving such memory cells.
Note that each memory cell of a DRAM usually consists of a capacitor for storing data and an FET (field effect transistor) for writing and reading data to and from the capacitor. The capacitor is formed by using the junction capacitance of an FET.
An SRAM employs flip-flop memory cells each consisting of six FETs. This SRAM is hardly minimized because each memory cell needs an area for the six FETs.
Japanese Unexamined Patent Publication Nos. 5-234361 and 5-235291 disclose examples of a semiconductor memory employing memory cells each being small and consisting of a small number of elements, and a method of writing and reading data to and from such memory cells.
These disclosures form each memory cell from a double-emitter transistor, which has two base-emitter junctions each having a negative differential characteristic to provide a bistable state. Data "1" and "0" are allocated to the two stable states, respectively. The bistable state is not broken even when voltages are separately applied to a bit line, word line, and ground line connected to the memory cell. When the memory cell sustains data, no current flows through a base-collector junction having a threshold characteristic.
When given voltages are simultaneously applied to the bit and word (ground) lines of a given memory cell, a current flows through the base-collector junction of the memory cell depending on one of the data storage states, or the data storage states are switched from one to another. Namely, it is possible to write and read data to and from a selected memory cell.
In this way, forming each memory cell with a double-emitter transistor realizes a high-integration SRAM.
To read a memory cell of the SRAM, a current flowing through a corresponding bit line is sensed. This current must be below a peak current to avoid a destructive read operation. Namely, this current determines a memory reading speed. On the other hand, the power consumption of each memory cell is determined by a valley current. Accordingly, the product of speed and power consumption of a memory cell is determined by the peak-valley ratio of a resonance tunnel of the memory cell.
To write data to a memory cell of the SRAM, a potential difference exceeding the forward and reverse breakdown voltages of the memory cell must be applied to the collector and emitters thereof. In this regard, the lower the breakdown voltages, the better. The breakdown voltages, however, must be high when the memory cells are arranged adjacent to one another.
The problem in the prior art will be explained later in detail, with reference to the accompanying drawings.